Senior Engineer, FPGA & ASIC System Architecture, meoSphere

Senior Engineer, FPGA & ASIC System Architecture, meoSphere

The job responsibilities outlined in this document are not exhaustive and may evolve over time and be reviewed according to business needs.

PROGRAMME DESCRIPTION meoSphere is the next generation of SES’s Medium Earth Orbit (MEO) satellites, delivering secure connectivity services for governments, enterprises, and commercial customers worldwide, while enabling high-speed broadband to eliminate connectivity gaps.

To accelerate development, improve quality, and increase vertical integration, SES is bringing key payload development and integration capabilities in-house within a state-of-the-art manufacturing and test environment.

ROLE DESCRIPTION SUMMARY

We are seeking an experienced Senior Engineer, FPGA & ASIC System Architecture to drive the architecture, strategy, and delivery of advanced digital payload and radio unit solutions, based on RFSoC and AMD FPGA devices, as well as ASIC technologies.

The successful candidate will act as a technical authority across multiple programs, contributing to the development of FPGA/RFSoC/Processor-based subsystems forming part of SES’s high-throughput communication systems (payloads, digital beamforming antennas, and radio units), ensuring alignment with end-to-end system requirements

PRIMARY RESPONSIBILITIES / KEY RESULT AREAS

Define and own FPGA and ASIC system architectures for RF and digital communication subsystems across multiple programs

Drive architecture strategy and design consistency, ensuring reuse and scalability across platforms

Translate system-level requirements into detailed architecture specifications, including:

Clock and reset strategies

Interface definitions

Low-level register maps

Architect and specify advanced digital signal processing chains, including:

Beamforming

Digital Front-End (DFE)

Up/down conversion chains

Crest Factor Reduction (CFR)

Define integration of ADC/DAC, IF signal generation, and RF signal paths, ensuring alignment with RF front-end constraints

Lead high-speed data interface architecture, including Ethernet, eCPRI, and RF over Ethernet solutions

Ensure compliance with relevant standards such as 3GPP (5G NR, FR2) and Radio Unit architectures

Provide technical leadership across multiple FPGA and ASIC development projects, including coordination of architecture and design activities

Lead and mentor RTL design teams, driving design quality, partitioning, and implementation strategies

Own ASIC and FPGA requirements management, ensuring traceability, completeness, and alignment with system objectives

Define and drive verification strategies and plans, ensuring robust validation from simulation to system-level testing

Drive hardware bring-up, integration, and debugging activities, supporting cross-domain issue resolution

Perform and validate FPGA resource estimation and performance analysis, optimizing for throughput, latency, power, and scalability

Contribute to technical roadmap definition and risk mitigation strategies, including prototyping and performance validation

Act as a technical authority and decision maker by leading complex technical activities across multiple programmes

QUALIFICATIONS & COMPENTENCIES

Master’s degree or PhD in Electrical Engineering, Telecommunications, Computer Engineering, or a related field

Significant experience (typically 10+ years) in FPGA and/or ASIC-based system design, including architecture roles

Fluency in English; other languages are an asset

Proven hands-on experience with:

AMD/Xilinx RFSoC or similar FPGA platforms

Complex DSP-based systems and high-performance digital architectures

Strong expertise in:

RF digital signal processing (beamforming, DFE, conversion chains)

ADC/DAC interfacing and IF signal processing

Multi-clock domain and high-speed digital design

Solid knowledge of:

High-speed interfaces (Ethernet, JESD, eCPRI)

RF system integration and Radio Unit design

Experience working with:

3GPP 5G NR / FR2 standards

RF over Ethernet and fronthaul architectures

Proven ability to:

Translate high-level requirements into structured architectures

Hands-on experience in:

Hardware bring-up, integration, and debugging

Competencies

Strong analytical and problem-solving mindset

Ability to work in a multidisciplinary and international environment

Structured, rigorous, and strategic approach to engineering

Strong communication and leadership skills, with ability to influence at system and program level

Proactive, autonomous, and capable of managing multiple high-impact priorities

Strong documentation skills, including:

Architecture specifications

Verification plans

Technical reports

OTHER KEY REQUIREMENTS / COMMENTS

The candidate must be eligible for a “SECRET” security clearance, in accordance with the national regulations as well as EU/ESA/NATO equivalents

Willing to work at least 60% onsite from office

Travel as required for project realization purposes

Embark on a career with us, where diversity isn't just a buzzword – it's our driving force. We are crafting a workplace mosaic that values every hue, background, and perspective. Join a global team where inclusivity sparks innovation, and individuality is not only embraced but celebrated. At SES we are committed to hiring inspiring individuals from all backgrounds. We take great pride in creating safe and inclusive processes and we support the recruitment, retention, and evolution of all employees irrespective of gender, colour, race, ethnicity, religion, sexual orientation, disability, veteran or marital status, background or walk in life.

SES and its Affiliated Companies are committed to providing fair and equal employment opportunities to all. We are an Equal Opportunity employer and will consider all qualified applicants for employment without regard to race, color, religion, gender, pregnancy, sex, sexual orientation, gender identity, national origin, age, genetic information, protected veteran status, disability, or any other basis protected by local, state, or federal law.

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